This invention relates to an MOS semiconductor circuit.
A dynamic RAM (DRAM) needs a periodic refresh operation or data hold operation. Many of recent DRAMs automatically initiate a refresh operation when they are not accessed, i.e., when they are in a standby mode. This type of a RAM has a refresh timer provided on the same chip, and this refresh timer measures the time interval between refresh operations to regularly trigger the refresh operation. In general, the refresh timer is constructed using a ring oscillator.
FIG. 1 illustrates a convention ring oscillator used as refresh timer.
The ring oscillator comprises six CMOS inverters I1 to I6 each having one of P-channel MOS transistors P1 to P6 coupled in series with a corresponding one of N-channel MOS transistors N1 to N6 between a power source terminal VDD of a high potential and a reference voltage terminal VSS (ground potential=0 V) of a low potential. The first five CMOS inverters I1 to I5 are coupled in ring, and the output of inverter I5 is coupled to the last CMOS inverter I6, which serves as a wave shaper. These inverters I1 to I6 have their respective output nodes S1 to S6 coupled to parasitic electrostatic capacitors C1 to C6, respectively.
When the ring oscillator is used as a refresh timer, its oscillation period is between, for example, 10 .mu.s and 100 .mu.s and its dissipation power determines the dissipation power of a DRAM in standby mode. Therefore, it is desirable to reduce the dissipation power of the ring oscillator itself as low as possible.
In the ring oscillator shown in FIG. 1, the constituents of each of the CMOS inverters coupled in ring, e.g., P-channel MOS transistor P1 and N-channel MOS transistor N1 of inverter I1 are designed to have a long channel length L so that these transistors each have a small conductance. For instance, their channel width W is about 2 .mu.m while the channel length L is 200 .mu.m. In contrast, transistors P6 and N6 constituting wave-shaping inverter I6 are designed to have a relatively large conductance; for instance, their channel width W is as wide as 100 .mu.m. This wave-shaping inverter I6 drives another circuit (not shown) and electrostatic capacitor C6 coupled to its output node S6 has a capacitance as high as 5 pF.
The aforementioned ring oscillator is used not only as the refresh timer, but also in a base-plate bias circuit that provides a base-plate bias voltage on chip.
When the ring oscillator is used as a refresh timer, it is not desirable that its oscillation frequency easily varies with a change in the ambient temperature, the voltage in use, manufacturing processes, each the like. This is because as the oscillation frequency increases, the standby current also increases. FIGS. 2 and 3 respectively depict the temperature characteristic of the oscillation frequency and the dependency of the oscillation frequency on the power source voltage in the prior art ring oscillator. As indicated by the characteristic of FIG. 2, the oscillation frequency varies about 30-40% between 0.degree. C. and 85.degree. C. As should be clear from the characteristic curve of FIG. 3, the oscillation frequency also varies about 30% when the power source voltage VDD varies between 4 V and 6 V. In the memory cells of a DRAM, the leak current increases at high temperatures and the number of charges which can be accumulated in the memory cells decreases with a low power source voltage. Accordingly, the refresh timer requires such a characteristic that the oscillation frequency is high at high temperature and low power source voltage. However, the prior art refresh timer actually has the contrary characteristics as shown in FIGS. 2 and 3. Therefore, according to the prior art, the refresh timer is designed to have a minimum allowable frequency at high temperatures and low power source voltages in order to ensure data holding even at these temperature and voltage levels. Consequently, the refresh timer oscillates at a higher frequency at low temperatures and high power source voltages, thus significantly increasing the standby current. Although the refresh interval need not be short in these temperature and voltage conditions, the refresh operation is executed frequently and thus wastefully because the refresh timer oscillates at a high frequency. Further, the standby current increase by 140% (due to the temperature change) .times.130% (due to the power source voltage change) of what is necessary and becomes about 180% of the proper amount, thus increasing the dissipated power. With variations in the manufacturing processes considered, the actual standby current may be two to three times the proper standby current.
Furthermore, since transistors P1 and N1 of inverter I1 have a long channel length L so as to have a small conductance, the area occupied by each inverter on an integrated chip is above 10000 .mu.m.sup.2, thus undesirably increasing the overall chip area.
The prior art circuit also has another shortcoming as follows.
FIG. 4 shows the waveforms of the output voltages at output nodes S5 and S6 of the respective inverters I5 and I6 of the ring oscillator shown in FIG. 1. The variation in the output voltage of inverter I5 at node S6 is considerably gentle as compared with the variation in the output voltage of inverter I6 at node S6. For instance, the time interval between t1 where the output voltage at node S5 is VSS and t2 where it is increased to the threshold voltage VTN of the N-channel MOS transistor, is 10 .mu.s.
Denoting the threshold voltage of P-channel MOS transistor P6 of inverter I6 as VTP, the threshold voltage of N-channel MOS transistor N6 and VTN and the time where the voltage at node S5 increases to the level (VDD-VTP) from the level VTN at t3, both transistors P6 and N6 are ON between time t2 and t3. Consequently, a current path is formed between source voltage terminal VDD and reference voltage terminal VSS through transistors P6 and N6. As the change in the voltage at output node S6 of inverter I5 is gentle, the time period in which the current flows between the voltage terminals is long. Assume now that the maximum current flowing between the voltage terminals in the ring oscillator is 5 mA and the channel widths W of transistors N6 and P6 are 100 .mu.m and 200 .mu.m, respectively. Then, the average current flowing in inverter I6 is 50 .mu.A, making it difficult to attain a low dissipation power due to the presence of inverter I6.
If the wave-shaping inverter I6 is omitted or the conductances of transistors P6 and N6 are reduced, the current path between the voltage terminals would disappear or the current would be reduced. However, in this case, the same phenomenon would in turn occur at the first stage of another circuit (not shown) which is driven by the output signal of inverter I6. Thus, the dissipation power cannot be reduced. Although inverter I1 is also driven by the output signal of inverter I6, its conductance is as low as 1/10000 of that of the wave-shaping inverter I6 so that the current flowing between voltage terminals of inverter I1 is negligible.
In short, the prior art circuit has some shortcomings such that the temperature and voltage characteristics cannot be flexibly set, the dissipation power and the chip area cannot be reduced as desired, and the oscillation frequency is not stable with respect to a change in temperature, voltage and manufacturing processes.